Low-overhead thermally resilient optical network-on-chip architecture

Publication date: Available online 29 March 2019Source: Nano Communication NetworksAuthor(s): Melika Tinati, Somayyeh Koohi, Shaahin HessabiAbstractIntegrated silicon photonic networks have attracted a lot of attention in the recent decades due to their potentials for low-power and high-bandwidth communications. However, these promising networks, as the future technology, are drastically susceptible to thermal fluctuations, which may paralyze wavelength-based operation of these networks. In this regard, precise addressing of thermally induced faults in optical networks-on-chip (ONoCs), as well as revealing practical methods to tackle this challenge will be a break-even point toward implementation of this technology. In this paper, thermal variation is investigated through analyzing on-chip power distribution, which is addressed by power profile of SPEC 2006 benchmark applications. Based on these assessments, herein we propose a low-power thermal-resilient optical network-on-chip (The-RONoC) architecture that significantly mitigates routing faults in ONoC. Utilizing a corrective unit in this architecture, 50% of the thermally induced switching faults are recovered with the cost of less than 2% area overhead. In addition, up to 42% performance improvement is achieved through this architecture in comparison to the basic architecture. Finally, we explore scalability of The-RONoC based on formal SNR analysis, as well as power consumption and the probability of optical transmission...

Source: Nano Communication Networks - March 30, 2019 Category: Nanotechnology Source Type: research