H2WNoC: A honeycomb hardware-efficient wireless network-on-chip architecture

Publication date: Available online 30 January 2019Source: Nano Communication NetworksAuthor(s): Mohammad Alaei, Fahimeh YazdanpanahAbstractNetwork-on-chips (NoCs) have emerged as communication backbones for enabling massive parallelism and high degree of integration in many-core chips. In spite of the advantages of conventional NoCs, wired multi-hop links impose limitations on NoCs performance by long delay and high power consumption especially in large systems. To alleviate these problems, different solutions such as wireless network-on-chip (WiNoC) designs have been proposed. WiNoCs benefit from long-range, high bandwidth and low power wireless links to solve problems corresponding to wired communications. Most of the WiNoC architectures have been designed based on mesh topology, while, honeycomb topology provides more energy-efficient NoC architecture with higher throughput than mesh topology, but, as we will show, a honeycomb-based WiNoC, by itself, does not reduce the amount of utilized hardware resources and delay. In this paper, we propose a hardware-efficient WiNoC with honeycomb topology, namely, H2WNoC aiming at reducing hardware resources, network cost, delay, and also energy consumption. Considering different performance parameters, cycle-accurate-based evaluations are performed for the proposed architecture; H2WNoC is compared with the traditional mesh WiNoC, as the baseline, and also with three state-of-the-art WiNoC architectures. Furthermore, design space expl...

Source: Nano Communication Networks - January 30, 2019 Category: Nanotechnology Source Type: research