Improved e-IpDFT for Synchrophasor Estimation implemented in an FPGA-based Controller

Publication date: Available online 27 April 2016 Source:Perspectives in Science Author(s): Arpan Malkhandi, Tirthadip Ghose Synchronized Phasor measurement units (PMU) are the essential entity for measurement, control and automation of the grid and are experiencing a constant technological advancement. Modification and evolution of International PMU Standards (i.e. the IEEE C37.118) are helping in the aspects of Intelligence, Reliability and Accuracy of these smart electronic devices. Accurate Phasor estimation is very important for real-time implementation of PMU in the existing power grid. In this respect, this paper proposes an Improved Enhanced Interpolated Discrete Fourier Transform (e-IpDFT) technique of Synchrophasor estimation by incorporating Sample Value adjustment. The proposed algorithm is implemented through LabVIEW and the robustness and accuracy of the new algorithm in presence of noise and DC offsets are compared with the exiting algorithms. The proposed algorithm in dumped in the FPGA based NI cRIO controller programmed through the platform of LabVIEW. The paper also gives a detailed architecture of the algorithm implementation inside an FPGA-based controller. Finally the paper explores the standard compliance of the PMU accordingly.

Source: Perspectives in Science - April 27, 2016 Category: Science Source Type: research