Performance Analysis of Alternate Repeaters for On-Chip Interconnections in Nanometer Technologies

Publication date: 2015 Source:Procedia Materials Science, Volume 10 Author(s): S. Rajendar, P. Chandrasekhar, M. Asha Rani, R. Naresh As the geometries of integrated circuits continue to shrink into the deep nanometer regime, the impact of on-chip interconnects is dominant on the overall system performance. This paper explores the power-delay trade-off in alternate repeater insertion techniques. The repeaters are placed along global on-chip interconnects to compensate the loss in the wires and to regenerate the signal strength. All the repeater insertion techniques with 3-pi RC distributed interconnect model are implemented at 45nm and 180nm technology with supply voltage operated at 1GHz. The performance metrics considered to compare the alternate repeated interconnects are power dissipation, propagation delay and power-delay-product (PDP).
Source: Procedia Materials Science - Category: Materials Science Source Type: research